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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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155Mb/s / 622Mb/s Transmitter (Multiplexer) with Clock Generation
The MC10SX1405 transmitter (Tx) chip is an integrated serialization SONET OC-3 (155.52Mb/s) and OC-12 (622.08 Mb/s) interface device. It generates the line rate clock and performs parallel-to-serial conversion in conformance with SONET/SDH transmission standards. High performance and low power is achieved with MOSAIC VTM, Motorola's most advanced high-performance silicon Bipolar process. A companion de-serialization (Rx) chip, the SX1401, is also available.
MC10SX1405
TRANSMITTER (MULTIPLEXER) WITH CLOCK GENERATION
* Selectable eight or four bit parallel interface * Performs parallel-to-serial conversion of four 38.88 Mbit/s or eight
19.44 Mbit/s inputs to a 155.52 Mbit/s OC3 serial data output
* Performs parallel-to-serial conversion of eight 77.76 Mbit/s inputs to a
622.08 Mbit/s OC12 serial data output
* Integrated PLL and VCO to generate the line-rate clock from a sub-rate
reference clock
* Multiple configurations for parallel interface timing provide system
design versatility * Provides PLL Frequency Control Monitor and Out-of-Lock Indicator * Provides parity verification of the OC3/OC12 serial output stream * Single supply operation (+5V) APPLICATIONS
FJ SUFFIX 52-LEAD CLCC PACKAGE CASE 778B-01
* * * *
SONET/SDH-based transmission systems, modules, test equipment ATM using SONET Add drop multiplexers Other (non-SONET) data rate transmission systems
TX SX1405 Parallel Data and Control
Laser Driver SX1130
Laser
CONTROL LOGIC
RX SX1405
Post Amp SX1125
PIN
Figure 1. Typical OC3/OC12 Electro-Optical Interface
This document contains information on a new product. Specifications and information herein are subject to change without notice. 12/97
(c) Motorola, Inc. 1997
1
REV 0.3
Optical Interface
MC10SX1405
PARALLEL DATA INPUT DI1:8
DIFFERENTIAL TX OUTPUT
SOP RETIME FF EPI PARITY CHECK RETCK PLLCK OC3 OC12 Interface VARCK REFCK 2 2 PHASE-LOCKED LOOP MC10SX1405 FCM OOL EO CONTROL SYSTEM 2 DIV 8 PERR RETIME FF MUX SOM LASER DRIVER
Figure 2. MC10SX1405 Simplified Block Diagram
SX1405 Theory of Operation Operation of the SX1405 is straightforward. Parallel data is input to the device. Serial-to-parallel conversion is performed. Then the serial data is output at the selected line rate clock. The 78 MByte/s or 19 MByte/s parallel data is converted into a bit-serial 622 Mbit/s or 155 Mbit/s data stream. The on-chip PLL generates the 622 MHz or 155 MHz line rate clock from a subrate clock. For testing and applications which provide an external high-frequency bit clock, the internal clock generation PLL may be bypassed. SX1405 Block Diagram Functional Description
Parallel to Serial Conversion In OC3 mode, converts a 4-bit (Nibble) 38.88 Mb/s or 8-bit (Byte) 19.44 Mb/s input to a differential 155.52 Mb/s serial data output. In OC12 mode, converts an 8-bit 77.76 Mb/s input to a differential 622.08 Mb/s serial data output. The input data is loaded into the Retime FF's by the Retiming Clock RETCK. Then the data is loaded into a shift register by PLLCK. The data shifted out is ordered MSB (DI1) first and LSB (DI8 or DI4) last. Parity Check The parity check provides a means of verifying the integrity of the parallel to serial converter with minimal overhead. The parity of the serial output data stream is compared to the value of the Even Parity Input (EPI). If a parity error is deteced, the Parity Error (PERR) output is set HIGH. The PERR pin has an Open Collector TTL Output and must be given a falling edge to reset the parity error detector.
SX1405 Control Signals Reset (RSTN) - Used for testing and verification, the TTL outputs are set to Tri-State and all divider flip-flops and the parity generator are reset when RSTN = LOW. This also sets PERR HIGH and PERR must be given a falling edge to reset the parity error detector for normal operation. An internal pull-up is provided on RSTN allowing the device to operate normally if RSTN is not used. Low Speed Select (LSS) - Selects data rate. LOW = OC-12 (622.08 Mb/s), HIGH = OC-3 (155.52 Mb/s). An
Phase Locked Loop
The on-chip Phase Locked Loop (PLL) synthesizes the internal bit rate clock from the 19.44 / 38.66 / 77.78 MHz input reference clock. The PLL consists of a phase / frequency detector, loop filter, and Voltage Controlled Oscillator (VCO) nominally operating at 1.2 GHz. Dividers provide the internal clocks and a sub-rate clock output PLLCKP/PLLCKM (differential PECL) for phase comparison. REFCK/REFCKM is the differential input PLL reference clock. The feedback, to close the loop of the PLL, is VARCK/VARCKM, the differential input variable clock. Both the REFCK and VARCK inputs can be driven by TTL levels if the "minus" input (REFCKM and VARCKM) are left open. An Out Of Lock indicator (OOL) is driven HIGH if the PLL is not frequency locked with the input reference clock.
MOTOROLA
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1405
internal pull-up is provided on LSS allowing the device to operate in OC-3 mode if LSS is not used. Nibble / Byte Select (NBB) - In OC-3 mode, selects between 4-bit (Nibble) and 8-bit (Byte) parallel data input format. LOW = Byte, HIGH = Nibble. An internal pull-up is provided on NBB allowing the device to operate in Nibble mode if NBB is not used. External Clock Select (ECSN) - Allows external high-frequency bit clock to be applied and bypasses the internal clock generation circuit. LOW = External bit clock. An internal pull-up is provided on ECSN allowing the device to operate normally if ECSN is not used. VCO Frequency Control Monitor (FCM) - Single ended reference voltage output generated from the VCO control voltage. Typically 1.25V and varying from 0.25V to 2.25V. Out of Lock Indicator (OOL) - Is set HIGH if the PLL is not frequency-locked to the input reference clock.
3 AVCC
45 AVCC
8 VCC
13 VCC
23 VCC
36 VCC
38 VCC
27 VCCT
32 VCCO
C1
R1
49 52 FILTN 1 FILTC SX1405 VBR2 47 VBR4 FILTP VBR3 VEET AVEE AVEE 46 VEE VEE VEE VBR1 48
0.1F 2k
C2
R2
2
0.1F
OC3 Mode C2, C3 = 4700pF R1, R2 = 1k OC12 Mode C2, C3 = TBD R1, R2 = TBD
15
18
41
6
50
29
Figure 3. SX1405 Typical Operating Circuit
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MOTOROLA
MC10SX1405
46 VBR3 VBR2 VBR1 AVEE N/C FILTN FILTC FILTP AVCC N/C FCM AVEE VBB 47 48 49 50 51 52 1 2 3 4 5 6 7 8 VCC
45
44
43
42
41
40
39
38
37
36
35
PLLCKM 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PLLCK VCCO SOM SOP VEET EPI VCCT OOL DI1 DI2 VCC DI3 DI4 20 DI5
9 REFCKM
10 REFCK
11 VARCK
12 VARCKM
13 VCC
14 RETCK
15 VEE
16 DI8
17 DI7
18 VEE
Figure 4. MC10SX1405 52-Lead Pinout (Top View)
MOTOROLA
4
DI6
PLLCKP 19
PERR
ECSN
RSTN
AVCC
VBR4
VCC
VCC
ECK
NBB
VEE
LSS
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1405
Table 1. SX1405 Pin Descriptions
Name TTL Compatible I/O RETCK DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 OOL EPI PLLCK RSTN LSS NBB ECSN PERR PECL Compatible I/O VBB REFCKM REFCK VARCK VARCKM SOP SOM PLLCKM PLLCKP ECK Analog I/O FCM VBR4-VBR1 FILTN FILTC FILTP Power and Ground Pins AVCC AVEE VCC VEE VCCT VEET VCCO Reserved N/C 4, 51 No Connection 3, 45 6, 50 8, 13, 23, 36, 38 15, 18, 41 27 29 32 Analog +5V Supply Analog 0V Supply PECL +5V Supply PECL 0V Supply Output TTL +5V Supply Output TTL 0V Supply Output PECL +5V Supply 5 46-49 52 1 2 VCO Frequency Control Monitor VCO FIlter Pins Loop Filter Negative Loop Filter Common Loop Filter Positive 7 9 10 11 12 30 31 34 35 42 PECL Voltage Reference Output (3.7V Nominally) Differential Input Reference Clock Minus Differential Input Reference Clock Plus Differential Input Variable Clock Plus Differential Input Variable Clock Minus Differential Serial Data Output Plus Differential Serial Data Output Minus PLL Clock Out (19.44 / 38.88 / 77.76MHz) Minus PLL Clock Out (19.44 / 38.88 / 77.76MHz) Plus External Clock Input 14 16 17 19 20 21 22 24 25 26 28 33 37 39 40 43 44 Re-Time Latch Clock Parallel Data Input (Byte LSB) Parallel Data Input Parallel Data Input Parallel Data Input Parallel Data Input (Nibble LSB) Parallel Data Input Parallel Data Input Parallel Data Input (Byte and Nibble MSB) Out of Lock Indicator Output Even Parity Input PLL Clock Out (19.44 / 38.88 / 77.76MHz) Reset Input Low Speed Select Input Nibble / Byte Select Input External Clock Select Input Parity Error Output and Reset, Open Collector Pin No Description
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MOTOROLA
MC10SX1405
MAXIMUM RATINGS*
Symbol VCC, VCCO, VCCT, AVCC VIN IOUT IOUT-TTL TSTG Parameter Power Supply (VEE, VEET, AVEE, GVEE = 0V) Input Voltage (VEE, VEET, AVEE, GVEE = 0V) PECL Output Current TTL Output Current Storage Temperature Continuous Surge Value -0.5 to +6.5 -0.5 to +6.5 50 100 5 -50 to +175 Unit V V mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC, VCCO, VCCT, AVCC ICC TA TJ Parameter Power Supply (VEE, VEET, AVEE, GVEE = 0V) Device Current Drain Operating Temperature Junction Temperature Value 5V 5% 100 -40 to +85 125 Unit V mA C C
TTL DC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IIH IIL VOH VOL VIH VIL IOZ Characteristic Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Tri-State Current 2.0 0.8 50 REP, ROD EDO, OOL 2.5 2.5 0.5 Min Typ Max 20 -0.6 Unit A mA V V V V A Condition VIN = VCC VIN = 0.5V IOH = -2mA IOH = -300A IOL = 5mA
100E PECL DC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IIH IIL VOH VOL VIH VIL Characteristic Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage 0.5 3.98 3.19 3.93 3.19 4.19 3.45 4.19 3.43 Min Typ Max 200 Unit mA mA V V V V NOTE 1. NOTE 1. NOTE 1. NOTE 1. Condition
1. PECL levels are referenced to VCC and will vary 1:1 with the Power Supply. The Outputs are loaded with an equivalent 50 termination to +3.0V. The values shown are for VCC = VCCT = VCCO = AVCC = 5.0V.
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MC10SX1405
PLL COMPONENT CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IFILT Kdt ADV E VFCM Characteristic Loop Filter Currents (FILTP-FILTN) Combined Phase Detector TZA Gain Loop Filter Amplifier Large Signal Differential Voltage Amplification Phase Error FCM Amplitude Range FCM Locked PLL Range FCM Shorted EFCM KFCM RO fVCO FCM Error FCM Gain FCM Output Impedance VCO Frequency VCO Frequency Shorted KO KOVCC VCO VCO Gain VCC Supply (AVCC) Sensitivity VCO Phase Noise 700 1000 120 -80 -30 -90 220 Min 300 -500 45 100 -0.45 0.3 0.65 1.1 -100 0.45 5000 1244 1800 1450 260 80 250 0.45 2.2 1.85 1.4 100 0.55 Typ Max 500 -300 80 Unit A A/rad V/V radians V V V mV gain MHz MHz MHz/V MHz/V dBc/Hz dBc/Hz 2000 (1%) - EXT. R FILTP, FILTN Shorted 2000 (1%) - EXT. R 0 < fVCC < 10MHz at f = 1kHz at f = 1kHz FILTP, FILTN Shorted Condition PD Up PD Down
AC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V +5%)
Symbol tr, tf tr, tf Characteristic PECL Rise/Fall Time TTL Rise/Fall Time Min Typ Max 1.6 5.0 Unit nS nS Condition 20-80%, 50 to VCC-2V 20-80%, 50 to VCC-2V
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MOTOROLA
MC10SX1405
REFCK=RETCK 38.88MHz RID EPI INTERNAL 155MHz PLL=VARCK 38.88MHz (Locked to REFCK) Serial Data SOP/SOM 0 bits 0-3 of nibble n-2 parity of nibble n-2 bits 0-3 of nibble n-1 parity of nibble n-1 bits 0-3 of nibble n parity of nibble n
bits 0-3 of nibble n-1 3 2 1 0 3
bits 0-3 of nibble n 2 1 0
bits 0-3 of nibble n+1 3 2 1 0
bits 0-3 of nibble n+2 3 2 1 0 3
Figure 5. SX1405 Timing Diagram -- OC-3, 4 Bits
REFCK=RETCK 19.44MHz RID EPI INTERNAL 155MHz PLL=VARCK 19.44MHz (Locked to REFCK) Serial Data SOP/SOM 0 7 6 5 bits 0-7 of byte n-1 parity of byte n-1 bits 0-7 of byte n parity of byte n
bits 0-7 of byte n 4 3 2 1 0 7 6 5
bits 0-7 of byte n+1 4 3 2 1 0 7
Figure 6. SX1405 Timing Diagram -- OC-3, 8 Bits
REFCK=RETCK 38.88MHz RID EPI INTERNAL 622MHz PLL=VARCK 77.76MHz (Locked to REFCK) Serial Data SOP/SOM 0 7 6 5 bits 0-7 of byte n-1 parity of byte n-1 bits 0-7 of byte n parity of byte n
bits 0-7 of byte n 4 3 2 1 0 7 6 5
bits 0-7 of byte n+1 4 3 2 1 0 7
Figure 7. SX1405 Timing Diagram -- OC-12, 8 Bits
MOTOROLA
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1405
OUTLINE DIMENSIONS
FJ SUFFIX CLCC PACKAGE CASE 778B-01 ISSUE O
-A- R 0.51 (0.020)
M
TA
S
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION R AND N DO NOT INCLUDE GLASS PROTRUSION. GLASS PROTRUSION TO BE 0.25 (0.010) MAXIMUM. 4. ALL DIMENSIONS AND TOLERANCES INCLUDE LEAD TRIM OFFSET AND LEAD FINISH. DIM A B C D F G H J K N R S INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.200 0.017 0.021 0.026 0.032 0.050 BSC 0.090 0.130 0.006 0.010 0.035 0.045 0.735 0.756 0.735 0.756 0.690 0.730 MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 5.08 0.44 0.53 0.67 0.81 1.27 BSC 2.29 3.30 0.16 0.25 0.89 1.14 18.67 19.20 18.67 19.20 17.53 18.54
N
-B-
0.51 (0.020) F
M
TA
S
B
S
K H
C J
0.15 (0.006) G D 52 PL S 0.18 (0.007)
M
-T-
SEATING PLANE
TA
S
B
S
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ECLinPS and ECLinPS Lite DL140 -- Rev 3 9
MC10SX1405/D MOTOROLA

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